PCI Express and PCI: |
- Supports 1-lane 2.5 Gb/s PCI Express.
- Utilizes 100-MHz Differential PCI Express Common Reference
Clock
- Fully Compliant with PCI Express Base Specification, Revision
1.0a
- Packetized serial traffic with PCI Express split completion
protocol
- Automatic retry of bad packets
- 8b/10b signal encoding
- In-band interrupts and messages
- Support of message signaled interrupts
- Fully Compliant with PCI Local Bus Specification, Revision
3.0
- PCI Bus Power Management Interface r1.1 Compliant
- Texas Instruments TSB82AA2
- PCI burst transfers and deep FIFOs to tolerate large host latency
- Transmit FIFO—5K asynchronous
- Transmit FIFO—2K isochronous
- Receive FIFO—2K asynchronous
- Receive FIFO—2K isochronous
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IEEE 1394 Std Support: |
- Fully Supports Provisions of IEEE P1394b Revision 1.33+ at 1-Gigabit
Signaling Rates
- Fully Supports Provisions of IEEE 1394a.2000 and 1394.1995
Standard for High Performance Serial Bus
- Fully Interoperable With Firewire., i.LINK., and SB1394., Implementation
of IEEE Std 1394
|
1394 Bus Transfer Rate: |
- Provides two IEEE Std 1394b-2002 fully compliant cable ports
at 100/200/400/800 megabits per second (Mbits/s).
|
Fiber Optical Port: |
- With one Agilent HFBR-5912E (MT-RJ) Small Form Factor Fiber
Optic Transceiver.
- Compliant with Specifications for IEEE 802.3z/ Gigabit Ethernet
- 850nm VCSEL(Vertical Cavity Surface Emitting Laser)
- Maximum link lengths:
V 220 m Links in 62.5/125 gm MMF 160 MHz*km Cables
V 275 m Links in 62.5/125 gm MMF 200 MHz*km Cables
V 500 m Links in 50/125 gm MMF 400 MHz*km Cables
V 550 m Links in 50/125 gm MMF 500 MHz*km Cables
IEC 60825-1 Class 1/CDRH
VClass 1 Laser Eye Safe
|
Number of Ports: |
External:
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Power Management: |
D0, D1, D2, and D3 power states and PME events per the PCI Bus
Power Management Interface Specification
|
Bus Power Connector: |
Big IDE 4-pin DC Power Connector
|