PCI Express: |
- Standards compliant
- PCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0)
- PCI Express Base Specification, Revision 2.0 Errata
- Backward-compatible with the PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1) and PCI Express Base Specification, Revision 1.0a (PCI Express Base r1.0a)
- PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)
- Microsoft Vista®-compliant
- Supports Access Control Services
- Dynamic Link-width control
- Dynamic SerDes speed control
Note: Additional specifications, with which this product complies, are listed in Supplemental Documentation.
- High Performance
- Non-Blocking Internal architecture
- Full line rate on all Ports
- Cut-Thru latency – 190 ns for Link widths of x4 to x1
- Maximum Payload Size – 512 bytes
- performancePAKTM
- Read PacingTM (intelligent bandwidth allocation)
- Dual CastTM
- Dynamic Buffer Pool Architecture for faster credit updates
- PCI Express Power Management
- Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready,and L3 (with Vaux not supported)
- Conventional PCI-compatible Device Power Management states – D0 and D3hot
- Active State Power Management (ASPM)
- Quality of Service (QoS) support
- Two Virtual Channels (VC0 and VC1) per Port
- Eight Traffic Classes (TC[7:0]) per Port
- Weighted Round-Robin (WRR) Port and Virtual Channel (VC) arbitration
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OHCI (Open Host Controller Interface) |
- Enhanced with the OHCI 1.2 draft specification for 1394b-2002
PHY full operational compliance.
- OHCI 1.0 backwards compatible. Configurable via EEPROM to operate
in either OHCI 1.0 or OHCI 1.1 mode.
- 8 Kbyte isochronous transmit FIFO.
- 4 Kbyte asynchronous transmit FIFO.
- 8 Kbyte isochronous receive FIFO.
- 8 Kbyte asynchronous receive FIFO.
- Dedicated asynchronous and isochronous descriptor-based DMA
engines.
- Eight isochronous transmit contexts.
- Eight isochronous receive contexts.
- Supports parallel processing of incoming physical read and write
requests.
- Supports up to 48-bit addressing per OHCI specifica-tion for
the physical DMA transfers.
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1394b-2002 Link |
- Cycle master and isochronous resource manager capable.
- Supports 1394a-2000 and 1394b-2002 acceleration features.
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1394b-2002 PHY |
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Number of Ports: |
- Four External Bilingual ports with Screw Holes for thumbscrew locking Type 1394b Cable
- OHCI 3: Two 1394b Bilingual ports
- OHCI 2: One 1394b Bilingual port
- OHCI 1: One 1394b Bilingual port
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Bus Power Connector: |
- Big IDE 4-pin DC Power Connector
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