• Host Bus: PCIe x4 (4-lane) Gen2 (20 Gb/s)
  • Quad OHCI 1.2 Compliant IEEE 1394b host controllers
  • Designed with Late VG Protection
  • Four independent external Bilingual IEEE Std 1394b-2002 Cable Ports
    • Supports Bilingual Plug port with Jackscrew Type 1394b Cable

The FWBX4-PCIE4XE120 is a Quad OHCI IEEE 1394b (Firewire 800) to PCI Express x4 Gen2 Host Card.

FWBX4-PCIE4XE120 is designed with two key components.

  • 8-Lane, 8-Port PCI Express Switch.
  • OHCI 1.2 Compliant IEEE 1394b Single Chip Host Controller (4pcs).

MultipleVCs (Virtual Channels) on the PCI Express link provide native support for QoS (Quality of Service) transmission for real-time and multimedia applications in a standards-based framework, ensuring compatibility with current and future operating systems. Active-state power management allows dynamic power management during periods of reduced network activity.

Technical Specifications
PCI Express:
  • Standards compliant
    • PCI Express Base Specification, Revision 2.0 (PCI Express Base r2.0)
    • PCI Express Base Specification, Revision 2.0 Errata
    • Backward-compatible with the PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1) and PCI Express Base Specification, Revision 1.0a (PCI Express Base r1.0a)
    • PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)
    • Microsoft Vista®-compliant
    • Supports Access Control Services
    • Dynamic Link-width control
    • Dynamic SerDes speed control
      Note: Additional specifications, with which this product complies, are listed in Supplemental Documentation.
  • High Performance
    • Non-Blocking Internal architecture
    • Full line rate on all Ports
    • Cut-Thru latency – 190 ns for Link widths of x4 to x1
    • Maximum payload size set to 256 or 128
  • performancePAKTM
    • Read PacingTM (intelligent bandwidth allocation)
    • Dual CastTM
    • Dynamic Buffer Pool Architecture for faster credit updates
  • PCI Express Power Management
    • Conventional PCI-compatible Link Power Management states – L0, L0s, L1, L2/L3 Ready,and L3 (with Vaux not supported)
    • Conventional PCI-compatible Device Power Management states – D0 and D3hot
    • Active State Power Management (ASPM)
  • Quality of Service (QoS) support
    • Two Virtual Channels (VC0 and VC1) per Port
    • Eight Traffic Classes (TC[7:0]) per Port
    • Weighted Round-Robin (WRR) Port and Virtual Channel (VC) arbitration
OHCI (Open Host Controller Interface)
  • Enhanced with the OHCI 1.2 draft specification for 1394b-2002 PHY full operational compliance.
  • OHCI 1.0 backwards compatible. Configurable via EEPROM to operate in either OHCI 1.0 or OHCI 1.1 mode.
  • 8 Kbyte isochronous transmit FIFO.
  • 4 Kbyte asynchronous transmit FIFO.
  • 8 Kbyte isochronous receive FIFO.
  • 8 Kbyte asynchronous receive FIFO.
  • Dedicated asynchronous and isochronous descriptor-based DMA engines.
  • Eight isochronous transmit contexts.
  • Eight isochronous receive contexts.
  • Supports parallel processing of incoming physical read and write requests.
  • Supports up to 48-bit addressing per OHCI specification for the physical DMA transfers.
1394b-2002 Link
  • Support for calculation and checking of the cyclic redundancy check (CRC) on outgoing and incoming packets
  • Support for decoding the destination ID of incoming 1394 packets to determine if an acknowledge is needed.
  • Cycle master and isochronous resource manager capability
  • Support for 1394a-2000 and 1394b acceleration features
1394b-2002 PHY
  • IEEE 1394b-2002 compliant ports supporting 1394b speeds of 800 Mb/s and 400 Mb/s while maintaining backward compatibility to IEEE 1394a-2000 speeds of 100 Mb/s, 200 Mb/s, and 400 Mb/s over 4.5 m copper.
  • Full support for IEEE 1394a-2000 and 1394-1995 standard provisions for high-performance serial bus.
  • Registers to indicate power class modes.
  • Extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders.
  • While unpowered and connected to the bus, the device does not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port.
  • No need for an external filter capacitor for PLL.
  • Link-on as a part of the internal PHY core-link interface.
  • Arbitrated short bus reset.
  • Ack-accelerated arbitration and fly-by concatenation.
  • Connection debounce.
  • Multispeed packet concatenation.
  • PHY pinging and remote PHY access packets.
  • Port disable/suspend/resume.
  • PHY-link interface initialization and reset.
  • Support for the 1394a-2000 register set.
  • Fully interoperable with FireWire® and i.LINK® implementation of IEEE 1394-1995.
  • Cable power fail interrupt reported when voltage at TPCPS pin falls below 7.5 V.
  • Separate cable bias and driver termination voltage supply for each port provided.
Number of Ports:
  • Four External Bilingual ports with Screw Holes for thumbscrew locking Type 1394b Cable
    • OHCI 4: One 1394b Bilingual port
    • OHCI 3: One 1394b Bilingual port
    • OHCI 2: One 1394b Bilingual port
    • OHCI 1: One 1394b Bilingual port
Bus Power Connector: Either Big IDE 4-pin DC Power Connector or/and SATA 15pin Power Connector
Computer Platform
  • Computer with PCI Express slot (x4, x8, x16)
Physical Dimensions
  • 130(D) x 99[120](H)mm
Operating System Requirements
  • Windows 2000/XP/7/8/8.1 and Windows Server 2003
  • Mac OS 10.4.8 or later
  • Linux 2.6.X