| PCI Express: |
- Standards compliant
- PCI Express Base Specification, Revision 2.1
- Backward-compatible with the PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1) and PCI Express Base Specification, Revision 1.0a (PCI Express Base r1.0a)
- PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)
- Microsoft Windows 7®-compliant
- Dynamic Link speed (2.5 or 5.0 GT/s) negotiation
- Dynamic Link width negotiation
- High Performance
- Non-Blocking Internal architecture
- Full line rate on all Ports
- Cut-Thru packet latency of less than 250 ns between symmetric (x1 to x1)
- Maximum Payload Size – 256 bytes
- PCI Express Power Management
- Conventional PCI-compatible Link Power Management states – L0, L0s, L1, and L2/L3 Ready
- Conventional PCI-compatible Device Power Management states –D0, D1, D2, and D3hot
- Active State Power Management (ASPM)
- Quality of Service (QoS) support
- All Ports support one, full-featured Virtual Channel (VC0)
- All Ports support eight Traffic Classes (TC[7:0]) mapping, independently of the other Ports
- Weighted Round-Robin (WRR) Port arbitration
|
| OHCI (Open Host Controller Interface) |
- Enhanced with the OHCI 1.2 draft specification for 1394b-2002
PHY full operational compliance.
- OHCI 1.0 backwards compatible. Configurable via EEPROM to operate
in either OHCI 1.0 or OHCI 1.1 mode.
- 8 Kbyte isochronous transmit FIFO.
- 4 Kbyte asynchronous transmit FIFO.
- 8 Kbyte isochronous receive FIFO.
- 8 Kbyte asynchronous receive FIFO.
- Dedicated asynchronous and isochronous descriptor-based DMA
engines.
- Eight isochronous transmit contexts.
- Eight isochronous receive contexts.
- Supports parallel processing of incoming physical read and write
requests.
- Supports up to 48-bit addressing per OHCI specifica-tion for
the physical DMA transfers.
|
| 1394b-2002 Link |
- Support for calculation and checking of the cyclic redundancy check (CRC) on outgoing and incoming packets
- Support for decoding the destination ID of incoming 1394 packets to determine if an acknowledge is needed.
- Cycle master and isochronous resource manager capability
- Support for 1394a-2000 and 1394b acceleration features
|
| 1394b-2002 PHY |
- IEEE 1394b-2002 compliant ports supporting 1394b speeds of 800 Mb/s and 400 Mb/s while maintaining backward compatibility to IEEE 1394a-2000 speeds of 100 Mb/s, 200 Mb/s, and 400 Mb/s over 4.5 m copper.
- Full support for IEEE 1394a-2000 and 1394-1995 standard provisions for high-performance serial bus.
- Registers to indicate power class modes.
- Extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders.
- While unpowered and connected to the bus, the device does not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port.
- No need for an external filter capacitor for PLL.
- Link-on as a part of the internal PHY core-link interface.
- Arbitrated short bus reset.
- Ack-accelerated arbitration and fly-by concatenation.
- Connection debounce.
- Multispeed packet concatenation.
- PHY pinging and remote PHY access packets.
- Port disable/suspend/resume.
- PHY-link interface initialization and reset.
- Support for the 1394a-2000 register set.
- Fully interoperable with FireWire® and i.LINK® implementation of IEEE 1394-1995.
- Cable power fail interrupt reported when voltage at TPCPS pin falls below 7.5 V.
- Separate cable bias and driver termination voltage supply for each port provided.
|
| Number of Ports: |
- Three External Bilingual ports with Screw Holes for thumbscrew locking Type 1394b Cable
|
| Bus Power Connector: |
- Big IDE 4-pin DC Power Connector or SATA 15-pin Power Connector
|
