Host DP Downstream Port Connector pin Assignment |
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Pin |
Symbol |
Description |
1 |
REFCLKn |
Differential 100MHz Cable Reference Clock |
2 |
GND |
Ground |
3 |
REFCLKp |
Differential 100MHz Cable Reference Clock |
4 |
PETp0 |
Differential PCI Express Transmitter Lane 0 |
5 |
GND |
Ground |
6 |
PETn0 |
Differential PCI Express Transmitter Lane 0 |
7 |
PERp1 |
Differential PCI Express Receiver Lane 1 |
8 |
GND |
Ground |
9 |
PERn1 |
Differential PCI Express Receiver Lane 1 |
10 |
PETp1 |
Differential PCI Express Transmitter Lane 1 |
11 |
GND |
Ground |
12 |
PETn1 |
Differential PCI Express Transmitter Lane 1 |
13 |
CPWRON |
Power Valid Notification |
14 |
CPERST# |
Cable PERST# at Downstream Subsystem |
15 |
PERn0 |
Differential PCI Express Receiver Lane 0 |
16 |
SB_RTN |
Signal Return for Single Ended Sideband Signals (GND) |
17 |
PERp0 |
Differential PCI Express Receiver Lane 0 |
18 |
CWAKE# |
Power Management Signal for Wakeup Events |
19 |
CPRSNT# |
Used for Detection if a Cable is Installed |
20 |
PWR |
+3.3V Power (Optional) |
