| Upstream PCIe interface |
- 4-lane PCI Express
- PCIe Gen 1 (2.5GT/s)
- PCIe Gen 2 (5.0GT/s)
|
| PCIe Features |
- Standards compliant
- Compliant with PCI Express Base Specification Revision 2.1
- Compliant with PCI Express CEM Specification Revision 2.0
- Compliant with PCI-toPCI Bridge Architecture Specification Revision 1.2
- Compliant with Advanced Configuration Power Interface (ACPI) Specification
- PCI Power Management Spec r1.2
- PCI Express Power Management
- Link power management states: L0, L0s, L1, L2/L3 Ready, and L3
- Device states: D0 and D3hot
- Active state power management for L0s and L1 states
- Port Arbitration Round Robin (RR) and Weighted RR and Time-based Weighted RR
- Extended Virtual Channel capability
- Two Virtual Channels (VC) and Eight Traffic Class (TC) support
- Disabled VCs’ buffer is assigned to enabled VCs for resource sharing
- Independent TC/VC mapping for each port
- Provides VC arbitration selection: Strict Priority, Round Robin (RR) and Programmable Weighted Round-Robin
- Supports Isochronous Traffic
- Isochronous traffic class mapped to VC1 only
- Strict time based credit policing
- Supports “Cut-through”(Default) as well as “Store and Forward” mode for switching packets
- Peer-to-peer switching between any two downstream ports
- Supports up to 256-byte payload size
- Enhanced Features
- 150ns typical latency for packet running through switch without blocking
- Supports Access Control Service (ACS) for peer-to-peer traffic
- Supports Address Translation (AT) packet for SR-IOV application
- Supports OBFF and LTR
|
| Jumper |
Virtual Channel 1
Disable: The unused VC1 queues (buffer) can be reassigned to VC0 and enable each of the ingress ports to handle more data traffic bursts. This virtual channel resource relocation feature enhances the performance of the PCIe Switch further.
Enable: Isochronous traffic class mapped to VC1 only |
USB Features
(Renesas uPD720202, USB IF TID 380000043) |
- Compliant with USB 3.0 Specification Revision 1.0
- Compliant with Intel’s eXtensible Host Controller Interface (xHCI) specification Revision 1.0
- Supports UASP (USB Attached SCSI Protocol)
- Each USB port supporting SS/HS/FS/LS data rates (5Gbps/480Mbps/12Mbps/1.5Mbps)
- USB Data Transfer Rate
- Low-speed (1.5 Mbps)
- Full-speed (12.0 Mbps)
- High-speed (480.0 Mbps)
- Super-speed (5.0 Gbps)
|
| Number of USB Ports |
- Four independent USB 3.0 Cable Ports (Micro-B type Receptacle, USB IF TID 361000096)
|
| USB3 cable lock mechanism |
- Provides the threaded holes for the jack-screws of USB 3.0 Micro-B w/Jackscrew lock Cable
|
| USB Bus Power Source |
USB Bus Power Source is from PCIe 12V ( 12V Step-Down to 5V)
Note: Synchronous step-down regulator
- High Frequency, Synchronous, Rectified, Step-Down, Switch-Mode Converter
- Operates at High Efficiency Over a Wide Output-Current-Load Range
- Non-Latch OCP, OVP, and Thermal Shutdown
- Minimum 4A Output Current
- Up to 95% Efficiency
|
| USB Port Current-Limited Power Switch |
2.0A (70mΩ on-resistance) Single Channel Current-Limited Power Switch (UL File Number E322375)
The devices have fast short-circuit response time for improved overall system robustness, and have integrated output discharge function to ensure completely controlled discharging of the output voltage capacitor. They provide a complete protection solution for applications subject to heavy capacitive loads and the prospect of short circuit, and offer reverse current blocking, over-current, over-temperature and short-circuit protection, as well as controlled rise time and under-voltage lockout functionality. |
| Computer Platform Requirements |
Desktop computer equipped with a PCIe 2.0/3.0 x4, x8, x16 slot |
